UCIe (Universal Chiplet Interconnect Express)

UCIe (Universal Chiplet Interconnect Express) is an open die-to-die interconnect standard designed for chiplet-based architectures. Its primary goal is to enable chiplets from different vendors, manufactured on different process nodes and even by different foundries, to communicate seamlessly within the same package.

Often described as the equivalent of PCI Express for chiplet systems, UCIe aims to establish a common ecosystem for interoperable chiplets and heterogeneous integration.

History

The UCIe Consortium was launched in March 2022 by a group of leading semiconductor and technology companies, including:

• Intel
• AMD
• Arm
• Qualcomm
• Samsung Electronics
• TSMC
• Google
• Microsoft
• Meta

The consortium has since expanded to include hundreds of members across the semiconductor ecosystem, including IP providers, EDA vendors, packaging companies, foundries, and system developers.

Architecture

UCIe consists of three primary layers:

Physical Layer (PHY)

The PHY handles the electrical transmission of data between chiplets and includes:

• High-speed signaling
• Link initialization and training
• Clocking and synchronization
• Error detection
• Power management

Because communication occurs over very short distances inside a package, UCIe PHYs achieve significantly higher energy efficiency than traditional board-level interfaces.

Die-to-Die Adapter Layer

The Adapter Layer provides a reliable transport mechanism and includes:

• Packetization
• Flow control
• Error handling
• Retry mechanisms
• Link management
• Protocol multiplexing

This layer abstracts protocol-specific details from the underlying physical interface.

Protocol Layer

UCIe supports multiple upper-layer protocols, including:

• PCI Express (PCIe)
• Compute Express Link (CXL)
  • CXL.io
  • CXL.cache
  • CXL.mem
• Streaming protocols
• Vendor-specific protocols

This flexibility allows UCIe to support a wide range of applications, from AI accelerators to memory expansion devices.

Related Articles

• U-Can-Inject-Errors (UCIe): A Protocol-Aware Hardware Trojan for FPGA Chiplet Links
• The Road to 64G UCIe IP: What Designers Need to Know
• On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency and Low Cost Approach
• Multi-Die Health and Reliability: Synopsys and TSMC Showcase UCIe Advances
• Intel and Cadence Collaboration on UCIe: Demonstration of Simulation Interoperability

Related Blogs

• UCIe 3.0: Faster Links Are Only Half the Story
• UALink over UCIe 3.0: Maximizing Performance for Chiplet-based Designs
• Advancing UCIe Performance: Enabling 40G for Next-Generation Multi-Die Designs
• UCIe Full Signal Integrity Analysis Flow
• Synopsys Advances Die‑to‑Die Connectivity with 64G UCIe IP Tape‑Out

Related News

• ForwardEdge ASIC Announces UCIe 3.0 IP Solution to Accelerate Next-Generation Chiplet-Based ASIC Innovation
• Racyics UCIe PHY IP for GlobalFoundries 22FDX reaches silicon
• AMD to Bring UCIe Connectivity to Select AMD Versal Adaptive SoCs
• InPsytech Highlights UCIe Innovation at COMPUTEX with UCIe Live Demo and Ultra-high speed ONFI 6400 Development
• EXTOLL and Chip Interfaces introduce the Industry´s first Integrated UCIe IP Solution for GlobalFoundries FDX Technology