CEA-Leti Pushes Stacking Roadmap as AI Runs Into Memory and Power Limits

Pascal Vivet says AI systems need memory placed closer to compute, wider data paths, and earlier co-optimization.

By Pat Brans, EE Times | July 31, 2026 

As AI models grow, hardware designers face a new challenge: placing far more memory closer to processors, moving data with less energy, and cooling systems whose power density keeps rising. For Pascal Vivet, program manager for advanced programs at CEA-Leti, that challenge is pushing 3D integration and chiplet-based architectures from advanced packaging technologies into the center of AI system design.

“3D technology is key,” Vivet told EE Times, because it allows the industry to scale “horizontally, vertically, and to assemble the best technology for chiplet partitioning in an open ecosystem.”

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