RapidChiplet: How to Explore the Design Space of Inter-Chiplet Interconnects

By Patrick Iff, Benigna Bruggmann, Blaise Morel, Maciej Besta, Luca Benini, Torsten Hoefler
Scalable Parallel Computing Lab, SPCL @ ETH Zurich

Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet interconnect (ICI). The ICI design space is huge, as there are many degrees of freedom, such as the number, size, and placement of chiplets, the topology and bandwidth of links, the packaging technology, and many more. While ICI simulators are important to get reliable performance estimates, they are not fast enough to explore hundreds of thousands of design points or to be used as a cost function for optimization algorithms or machine learning models. To address this issue, we present RapidChiplet, a fast and easy to use ICI latency and throughput prediction toolchain. Compared to cycle-level simulations, we trade 0.25%–30.15% of accuracy for 427x–137,682x speedup.

Paper: https://arxiv.org/abs/2311.06081

Code: https://github.com/spcl/rapidchiplet