Packaging Matter: Extending Moore’s law with “re-aggregation”
By Sujit Sharan, Advanced Design and Technology Solutions, Intel Corporation
With the arrival of ChatGPT, Large Language Models (LLMs) have transformed AI into an interactive and accessible technology that recursively builds on its prior accomplishments, fueling a new gold rush era of applications. AI models have exploded in complexity and size, exerting demand pressure on both compute and memory. Over time, Moore’s law has yielded a roughly 2x increase in compute every 2 years, compared to the enormous 750x per year growth demand from the LLMs. Memory is an even trickier problem as it needs to address capacity, speed and cost of data transport. Packaging plays a pivotal role in this era, architecting bespoke solutions for a highly differentiated set of applications. We take a look at the role of disaggregation, chiplets and interconnects in enabling the future of AI and HPC and illustrate this with solutions that can help create unique functionality, performance, and cost while enabling reuse and modularity.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- Chiplets and Next-gen Packaging Technologies in University Education
- Why chiplet will transform the semiconductor ecosystem from design to packaging?
- Standards for Chiplet Design with 3DIC Packaging (Part 1)
- Standards for Chiplet Design with 3DIC Packaging - Part 2
Latest Videos
- The European Chip Ecosystem
- Scaling up AI Compute, Memory and Connectivity
- CURIE: A Cycle-Accurate and Synthesizable UCIe Interface for the Agile Design and Co-Simulation of Chiplets
- Federated Chiplet Design and Simulation
- Custom HBM as a System: Co-designing the Base Die, Die to Die Power, and Package Thermals for AI Accelerators