Coding approaches for increasing reliability and energy efficiency of 3D technologies
In this video, Prof. Alberto Garcia-Ortiz presents a low-power coding framework designed specifically for heterogeneous 3D ICs, where interconnect power is a major bottleneck. The framework integrates technology-aware energy models and real data statistics, delivering dynamic, configurable encoding strategies. Tests with realistic 3D profiles and ML workloads demonstrate up to 4.6× energy savings in NoC links with minimal area overhead.
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related Videos
- TSMC 3Dblox™: Unleashing 3D IC Innovations for the Next Generation of AI, HPC, Mobile and IoT
- AI-Driven Thermal Prediction for Enhanced Reliability in 3D HBM Chiplets
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- Chiplets and Next-gen Packaging Technologies in University Education
Latest Videos
- Accelerating Chiplet SoC Development with Standards-Based Frameworks and Automated Design Flows
- Qualcomm's Tony Pialis on Dragonfly and the Data Movement Wall
- From silos to system: Sujit Sharan on the cultural and technical shift 3D IC demands
- Advancing 3DIC Technologies to Propel AI Innovations
- Building Real Confidence in Chiplet Stacks with Evelyn Landman of proteanTecs