Breaking Down Die Size Barriers with Chiplets
Why are hyperscalers moving towards chiplet ecosystems?
Anu Ramamurthy, Associate Research Fellow from Microchip Technology, and Open Chiplet Economy Sub-Project Co-Lead for Open Compute Project, explains:
- Large die sizes are reaching their physical limits, requiring division into smaller chiplets
- Chiplet architecture helps maintain high yields and lower costs while achieving needed computational power
- OCP enables multiple vendors to participate in the chiplet marketplace, expanding beyond proprietary solutions
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Videos
- Unleashing Chiplet potential with BoW - "The Knot That Ties Chiplets Together"
- Getting Moore with Less: How Chiplets and Open Interconnect Accelerate Cloud-Optimized AI Silicon
- Chiplets tackle semiconductor barriers
- Rapid Innovation with Chiplets and FPGAs
Latest Videos
- From Transistors to AI: The Chiplet Revolution with Ramune Nagisetty
- Scaling AI with Chiplets & CPO
- Open Interconnect Innovations: A Deep Dive into the UALink Chiplet Specification Tutorial
- From chips to silicon destiny: The next wave of 3D IC
- How Chiplets are Helping to Democratize Semiconductor Design with Mohit Gupta, CEO of TYLsemi