Breaking Down Die Size Barriers with Chiplets
Why are hyperscalers moving towards chiplet ecosystems?
Anu Ramamurthy, Associate Research Fellow from Microchip Technology, and Open Chiplet Economy Sub-Project Co-Lead for Open Compute Project, explains:
- Large die sizes are reaching their physical limits, requiring division into smaller chiplets
- Chiplet architecture helps maintain high yields and lower costs while achieving needed computational power
- OCP enables multiple vendors to participate in the chiplet marketplace, expanding beyond proprietary solutions
Related Chiplet
- High Performance Droplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
Related Videos
- Unleashing Chiplet potential with BoW - "The Knot That Ties Chiplets Together"
- Getting Moore with Less: How Chiplets and Open Interconnect Accelerate Cloud-Optimized AI Silicon
- Chiplets tackle semiconductor barriers
- Rapid Innovation with Chiplets and FPGAs
Latest Videos
- Coding approaches for increasing reliability and energy efficiency of 3D technologies
- AI-Driven Thermal Prediction for Enhanced Reliability in 3D HBM Chiplets
- Rearchitecting AI Infrastructure with General Purpose and Accelerator Chiplets
- UCIe Based Chiplet Ecosystem Interoperable Testbench for Multi Vendor IP Integration
- From ASIC Startups to Chiplets: Decades of Semiconductor Leadership and Innovation | Kash Johal