Breaking Down Die Size Barriers with Chiplets
Why are hyperscalers moving towards chiplet ecosystems?
Anu Ramamurthy, Associate Research Fellow from Microchip Technology, and Open Chiplet Economy Sub-Project Co-Lead for Open Compute Project, explains:
- Large die sizes are reaching their physical limits, requiring division into smaller chiplets
- Chiplet architecture helps maintain high yields and lower costs while achieving needed computational power
- OCP enables multiple vendors to participate in the chiplet marketplace, expanding beyond proprietary solutions
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Videos
- Unleashing Chiplet potential with BoW - "The Knot That Ties Chiplets Together"
- Getting Moore with Less: How Chiplets and Open Interconnect Accelerate Cloud-Optimized AI Silicon
- Chiplets tackle semiconductor barriers
- Rapid Innovation with Chiplets and FPGAs
Latest Videos
- A Physics-Informed Neural Network Surrogate for Runtime PDN and Dynamic Droop Prediction in 2.5-D Chiplet Integration
- A Chiplet Interface Model for System-Level PPA Exploration
- Zero trust in silicon: The new security imperative for chiplet-based 3D ICs
- Beyond the data pipe: Why connectivity IP is now the system-critical layer in every 3D IC
- An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration