Alphawave and Keysight: UCIe Compliance Validation Journey from System Simulation to Silicon
By Letizia Giuliano, Alphawave Semi
Alphawave Semi talks about how it uses Keysight Chiplet PHY Designer to validate its IP and chips for UCIe compliance.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- Introduction to UCIe Tutorial: Electrical, Form Factor, and Compliance
- Building an Interoperable Chiplet Ecosystem through Golden Die Validation with Pre Silicon Correlation
- Keysight UCIe Chiplet PHY Designer Demo
- Keysight Expands Chiplet Interconnect Support with UCIe 2.0 & BoW
Latest Videos
- Security of Multi chip ICs & Security Chiplets with Caliptra Building a Hardware Root of Trust
- System level standards for Multi vendor chiplet interoperability
- Die to Die Solutions for Optical Chiplets
- Building Interoperable AI Systems with Chiplets Arm Neoverse and Cadence in an Open Ecosystem
- Market Forecast for CPO and NPO