Keysight Expands Chiplet Interconnect Support with UCIe 2.0 & BoW
Keysight has expanded its Chiplet PHY Designer 2025 with support for UCIe 2.0 and BoW, enabling seamless chiplet interoperability for AI and data center applications. In this interview, Hui Su, High-Speed Digital Segment Lead at Keysight EDA, discusses the latest advancements in chiplet design, pre-silicon validation, and how this tool accelerates time-to-market while reducing costly re-spins.
Key Topics Covered:
- UCIe 2.0 & Open Compute Project BoW support
- Pre-silicon validation for high-speed chiplet interconnects
- Advanced QDR clocking scheme and systematic crosstalk analysis
- How AI and data centers benefit from chiplet technology
- Keysight’s presence at DesignCon 2025
Related Chiplet
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
Related Videos
- Blue Cheetah BlueLynx for Heterogeneous Integration: 16 Gbps Chiplet Interconnect IP for UCIe & BoW
- Keysight UCIe Chiplet PHY Designer Demo
- UCIe 2.0 Specification: Advancing an open ecosystem for on-package chiplet innovation
- Webinar on UCIe 2.0: Redefining the Chiplet Interoperability
Latest Videos
- A Chiplet Interface Model for System-Level PPA Exploration
- Zero trust in silicon: The new security imperative for chiplet-based 3D ICs
- Beyond the data pipe: Why connectivity IP is now the system-critical layer in every 3D IC
- An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration
- DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation