Keysight Expands Chiplet Interconnect Support with UCIe 2.0 & BoW
Keysight has expanded its Chiplet PHY Designer 2025 with support for UCIe 2.0 and BoW, enabling seamless chiplet interoperability for AI and data center applications. In this interview, Hui Su, High-Speed Digital Segment Lead at Keysight EDA, discusses the latest advancements in chiplet design, pre-silicon validation, and how this tool accelerates time-to-market while reducing costly re-spins.
Key Topics Covered:
- UCIe 2.0 & Open Compute Project BoW support
- Pre-silicon validation for high-speed chiplet interconnects
- Advanced QDR clocking scheme and systematic crosstalk analysis
- How AI and data centers benefit from chiplet technology
- Keysight’s presence at DesignCon 2025
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- Blue Cheetah BlueLynx for Heterogeneous Integration: 16 Gbps Chiplet Interconnect IP for UCIe & BoW
- UCIe 2.0 Specification: Advancing an open ecosystem for on-package chiplet innovation
- Webinar on UCIe 2.0: Redefining the Chiplet Interoperability
- On Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low-Power, High-Bandwith, Low-Latency and Low-Cost Approach
Latest Videos
- Agile Silicon Will Open Chiplet Architectures Keep Pace with Fast-Evolving AI Dataflows
- One Abstraction, Many Transports: Push-Mode Communication from Chiplet to Rack
- Advancing Chiplet Flexibility Updates in 2.0 OCE Transaction and Link Layer Specification
- GTC '26 - Berlin | Long-running, multi-tool Fuse Agents for 3D IC workflows
- Securing the Open Chiplet Ecosystem Defining a Common Security Architecture for FCSA