Scaling up AI Compute, Memory and Connectivity
Igor Elkanovich, CTO, GUC
Growing demand for AI performance drives scaling compute power, memory capacity and bandwidth, Scale-up bandwidth and radix with maximal power efficiency. 3D integration is a main approach to increase compute density. High bandwidth, low power and latency 3D interface allows flexible architectural partitioning across top and bottom dies. To support high current demand with minimal loss, vertical power delivery combines Voltage Regulator (VR) integration in PCB cavity under the chip, VRs in package substrate and in CoWoS-L interposer. 3D stacking of multiple DRAM layers over compute enhances architectural flexibility and memory bandwidth, reduces memory latency and improves power efficiency. Co-Packaged Optics (CPO) enables high bandwidth and radix power efficient system scaling, XPU platform with HBMs and 102Tbps Slow-Wide CPO optical engines is presented. Integration of advanced packaging technologies enables high performance and power-efficient AI processors of the future.
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