CURIE: A Cycle-Accurate and Synthesizable UCIe Interface for the Agile Design and Co-Simulation of Chiplets

Speaker: Prof. Thierry Tambe, Stanford University

Chiplet-based systems enable heterogeneous integration and independent scaling of compute and memory, but evaluating inter-die communication requires models that capture both cycle-level behavior and hardware implementation constraints. Existing UCIe models are mostly proprietary and sacrifice fidelity for abstraction, limiting quantitative system-level exploration and the path to hardware. We present CURIE (Configurable UCIe for Rapid Integration and Design Space Exploration), an open-source, synthesizable, cycle-accurate SystemC/HLS implementation of a UCIe 2.0 controller for agile design and co-simulation of chiplet-based systems. CURIE exposes configurable architectural parameters for exploring performance-efficiency tradeoffs and decouples application-specific protocol semantics from the UCIe transport layer, so custom packet layouts can be integrated, making it a reusable die-to-die building block across heterogeneous configurations. We demonstrate workload-aware exploration of disaggregated configurations by simulating a host processor integrated with an AI accelerator, while retaining a direct path to HLS-generated RTL. We synthesize CURIE in 16-nm FinFET to characterize its overhead, verify it against the specification at each controller layer and end to end, and further validate it through interoperability with an independently developed UCIe controller. SystemC AMS integration additionally captures channel-level effects. CURIE thus bridges cycle-accurate system exploration and synthesizable UCIe hardware for evaluating multi-chip systems.