Advanced Semiconductor Packaging Explained: Hybrid Bonding, Chiplets & Manufacturing Innovation
Advanced semiconductor packaging is rapidly becoming the key driver of performance, cost efficiency, and scalability in modern computing systems.
In this episode of the Semiconductor Leadership Podcast, host Salah Nasri sits down with Dr. TK Lee, founder of Launch Tech and a semiconductor packaging pioneer with more than 140 U.S. patents, to explore the technologies shaping the future of chip manufacturing.
Dr. Lee shares insights from decades of experience across Texas Instruments, Micron, and global R&D labs, discussing how packaging has evolved from a backend process into a system-level engineering discipline enabling AI, high-performance computing, and heterogeneous integration.
The conversation dives into:
- Hybrid bonding and chiplet architectures
- Panel-level vs wafer-level packaging
- Manufacturing scalability and process stability
- Substrate innovation and materials engineering
- Reliability challenges in advanced packages
- The skills future semiconductor engineers must develop
Dr. Lee also explains why innovation, multidisciplinary engineering, and system-level thinking will determine which companies lead the next era of semiconductor manufacturing.
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Videos
- Propelling AI forward through Advanced Packaging Creativity
- From ASIC Startups to Chiplets: Decades of Semiconductor Leadership and Innovation | Kash Johal
- Arm Viewpoints: Chiplets explained – the technology and economics behind the next wave of silicon innovation
- Podcast - A Modular Future: Chiplets, AI, and Advanced Packaging
Latest Videos
- A Chiplet Interface Model for System-Level PPA Exploration
- Zero trust in silicon: The new security imperative for chiplet-based 3D ICs
- Beyond the data pipe: Why connectivity IP is now the system-critical layer in every 3D IC
- An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration
- DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation