Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration
By Hayato Kitagawa 1, Ryosuke Sato 1, Sodai Ebiko 1, Atsushi Nagata 2, Chiwoo Ahn 3, Yeounsoo Kim 3, Jiho Kang 3, Akira Uedono 4, Fumihiro Inoue 5
1 Yokohama National University, Japan
2 Tokyo Electron Kyushu Limited, Japan
3 SK hynix Incorporation, Japan
4 University of Tsukuba, Japan
5 Yokohama National University, Japan

Abstract
Wafer bonding is a step in processing of state-of-the-art integration architectures in CMOS devices. Sufficiently high bonding strength and low distortion with high alignment accuracy are essential to realize these device structures. A challenge in realizing advanced architectures is reducing the thermal history associated with the bonding process. Although much research has been conducted on wafer bonding methods compatible with the latest semiconductor manufacturing processes, discussions on the interface mechanisms during low temperature annealing have been insufficient. In this study, plasma-activated bonding was carried out using SiCN, which is a major bonding dielectric material. The bonding strength and water remaining at the interface were subsequently evaluated. We found that a SiCN film achieved greater bonding strength after post bond annealing at a low temperature of 250 °C and completely consumed the interfacial water. Analyses of the surface and interface revealed the carbon bonding leads to great bonding interface by low-temperature annealing.
To read the full article, click here
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Technical Papers
- Self-Activated Direct Bonding with a Highly Polar Atomic-Layer-Deposited Film for 3D Integration
- Cu-Cu Hybrid Bonding for Chiplets Heterogeneous Integration
- Toward Multi-kW Power Delivery Methodologies for Advanced 3D Heterogeneous Integration
- Spiking Transformer Hardware Accelerators in 3D Integration
Latest Technical Papers
- Adaptive 3D Chiplet Architecture with Hybrid Wired–Wireless Interconnect for Energy-Efficient Heterogeneous Computing
- LLM-Augmented Bayesian Optimization with Adaptive Policies for Chiplet Design Space Exploration
- Divide and conquer: Scalable performance and energy in MCM GPUs
- A Composable AI-Accelerated Iterative Solver for 3D-IC Thermal Modeling
- QBX: A Compiler for 2-local Qubit Hamiltonian Simulation on Quantum Chiplets