ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM Training
By Kangbo Bai, Zhantong Zhu, Yifan Ding and Tianyu Jia
School of Integrated Circuits, Peking University, Beijing, China
Abstract
In large-scale distributed LLM training, communication between devices becomes the key performance bottleneck. Chiplet technology can integrate multiple dies into a package to scale-up node performance with higher bandwidth. Meanwhile, optical interconnect (OI) technology offers long-reach, highbandwidth links, making it well suited for scale-out networks. The combination of these two technologies has the potential to overcome communication bottlenecks within and across packages. In this work, we present ChipLight, a cross-layer multi-objective design and optimization method for training clusters leveraging chiplet and OI. We first abstract an architecture model for such complex clusters, co-optimizing chiplet architecture, training parallel strategy, and OI network topology. Based on such models, we tailor the design space exploration flow by combining both black-box and white-box methodologies. Evaluated by our experimental results, ChipLight achieves significantly improved training efficiency and provides valuable design insights for the development of future training clusters.
Index Terms — Chiplet, Optical Interconnect, LLM Training
To read the full article, click here
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Technical Papers
- Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation
- CHICO-Agent: An LLM Agent for the Cross-layer Optimization of 2.5D and 3D Chiplet-based Systems
- Exploring the Efficiency of 3D-Stacked AI Chip Architecture for LLM Inference with Voxel
- FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5D Systems
Latest Technical Papers
- Fengshui: Demystifying Chiplet Ecosystem and Bespoke Neural Network Accelerator Codesign
- Hardware Trojan Threats to Multi-Chiplet Photonic Neural Network Accelerators
- Mapping Dynamic, Hierarchical Quantum Circuits
- Chiplet-Based Techniques for Scalable and Memory-Aware Multiscalar Multiplication on Hardware Platforms
- A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators