ATSim: A Fast and Accurate Simulation Framework for 2.5D/3D Chiplet Thermal Design Optimization
By Qipan Wang 1,2, Tianxiang Zhu 1, Jiajia Cui 1, Yicheng Wei 1, Linxiao Shen 1, Zhe Cheng 1, Runsheng Wang 1,3,4, Ru Huang 1,3,4, Yibo Lin 1,3,4
1 School of Integrated Circuits, Peking University
2 Academy for Advanced Interdisciplinary Studies, Peking University
3 Institute of Electronic Design Automation, Peking University, Wuxi, China
4 Beijing Advanced Innovation Center for Integrated Circuits, Beijing, China

Abstract
This paper reviews the thermal challenges in 2.5D/3D chiplet integration systems and introduces ATSim, a simulation framework with applications to chiplet thermal optimization. ATSim enables fast and accurate thermal simulation for both steady-state and transient conditions. It supports nonlinear, heterogeneous, and anisotropic materials. The framework features a multilevel grid generation scheme based on a novel hybrid tree structure. Compared to mainstream academic and commercial tools, ATSim achieves high accuracy and efficiency, making it a powerful tool for evaluating and improving thermal designs, including applications like thermal-aware placement.
To read the full article, click here
Related Chiplet
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
Related Technical Papers
- DeepOHeat-v1: Efficient Operator Learning for Fast and Trustworthy Thermal Simulation and Optimization in 3D-IC Design
- 3D-ICE 4.0: Accurate and efficient thermal modeling for 2.5D/3D heterogeneous chiplet systems
- Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond
- ThermoDSE: A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators
Latest Technical Papers
- The Signal-Integrity Control Strategy of a TSV Array for a Chiplet-Based System
- ThermoDSE: A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators
- GPU-Accelerated Effective Resistance Analysis for 3D IC Power Delivery Network
- FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5D Systems
- Chiplet-Escape: An Efficient Obstacle-Avoiding Escape Routing Method for Die-to-Die Interconnections in Chiplet-Based Designs