Chiplever: Towards Effortless Extension of Chiplet-based System for FHE

By Yibo Du^1,3, Ying Wang^1,3, Bing Li⁴, Fuping Li^2,3, Shengwen Liang^2,3, Huawei Li^2,3, Xiaowei Li^2,3 and Yinhe Han^1,3
1 CICS, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
² SKLP, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
³ University of Chinese Academy of Sciences, Beijing, China 4Capital Normal University, Beijing, China

Fully Homomorphic Encryption (FHE) is one of the most promising privacy-preserving techniques that has drawn increasing attention from academia and industry due to its ideal security. Chiplet-based designs integrate multiple dies into the package delivering high performance and thereby are embraced by the resources-hungry FHE. Despite the chiplet-based system with various specialized accelerators, it falls short in supporting FHE with the novel polynomial operations. For a chiplet-based system that is not tailored for FHE, one common approach to support FHE is designing a new dedicated accelerator, However, this full design-and-build approach overlooks the existing abundant resources of accelerators in the system and incurs repeated customization and resource waste.

In this paper, we propose Chiplever, a framework enables effort-less extension of Chiplet-based system for FHE. We aim to fully harness the available resources in the room for efficient FHE. To achieve this, Chiplever introduces a specialized extension in I/O Chiplet guided by semantics matching and proposes an efficient allocator featuring specialized dataflow scheduling. Chiplever provides three-step mapping to achieve compiler-level to hardwarelevel support for FHE and optimizes the data communications.

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