Chiplet Technical Library

LEXI: Lossless Exponent Coding for Efficient Inter-Chiplet Communication in Hybrid LLMs

By Miao Sun, University of Wisconsin-Madison

March 17, 2026

Link Quality Aware Pathfinding for Chiplet Interconnects

By Aaron Yen, University of California

March 13, 2026

Effects of Poor Workload Partitioning on System Performance for Chiplet-Based Systems

By Peter Mbua, University of Florida

March 13, 2026

Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures

By Shuqing Luo, University of North Carolina

March 10, 2026

Advanced Packaging & Chiplet Design with Chipletz

By Stephen Newberry, Victor Kronberg, and Ching-Ping Wong

March 12, 2026

Integrated Photonics for the Next Generation of Glass Core Substrates

By Expert: Julian Schwietering

March 12, 2026

Photonic Wire Bonding: Bridging the Gaps in Photonic Packaging

By Wojciech Lewoczko-Adamczyk

March 3, 2026

Thermal Simulator for Advanced Packaging and Chiplet-Based Systems

By Yousef Safari

February 23, 2026

The Right Testing Strategy Can Save Designs

By Teradyne

February 24, 2025

Accelerating AI Chip Development with 3D Multi-Die Designs

By Synopsys

February 12, 2025

Scaling Connectivity for Chiplet-Based AI Systems

By Alphawave Semi

February 11, 2025

5 key reasons… Chiplet (die-2-die) interfaces require specialty I/O circuits and custom ESD protection

By Sofics

February 7, 2025