Chiplet Technical Library

Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators

By Zongle Huang, Tsinghua University

February 20, 2026

Scaling Routers with In-Package Optics and High-Bandwidth Memories

By Isaac Keslassy, Technion

February 18, 2026

TDPNavigator-Placer: Thermal- and Wirelength-Aware Chiplet Placement in 2.5D Systems Through Multi-Agent Reinforcement Learning

By Yubo Hou, A*STAR

February 16, 2026

Towards Scalable Multi-Chip Wireless Networks with Near-Field Time Reversal

By Ama Bandara, Universitat Politecnica de Catalunya

February 11, 2026

Cadence Chiplets Solutions: Helping you realize your chiplet ambitions

By David Glasco

February 19, 2026

2.5 D Heterogeneous Chiplet Packaging Challenge

By Vern Solberg

February 9, 2026

2026 Predictions from Alpahwave Semi, now part of Qualcomm

By Tony Chan Carusone

January 30, 2026

Arm Viewpoints: Chiplets explained – the technology and economics behind the next wave of silicon innovation

By Austin Lyons & Brian Fuller

January 21, 2026

The Right Testing Strategy Can Save Designs

By Teradyne

February 24, 2025

Accelerating AI Chip Development with 3D Multi-Die Designs

By Synopsys

February 12, 2025

Scaling Connectivity for Chiplet-Based AI Systems

By Alphawave Semi

February 11, 2025

5 key reasons… Chiplet (die-2-die) interfaces require specialty I/O circuits and custom ESD protection

By Sofics

February 7, 2025