Driving AI Innovation with Chiplet Standards
How are chiplet standards evolving to enable an open ecosystem? Jawad Nasrullah, CEO from Palo Alto Electron and Open Chiplet Economy Sub-Project Co-Lead for Open Compute Project, explains:
- Die-to-die communication standards like Bunch of Wires (BOW) are laying the foundation for modern chiplet interconnect specifications
- New standardized design languages like CCDXML enable cross-vendor tool compatibility for chiplet integration
- Development of chiplet socket standards addresses power delivery, bump maps, and mechanical specifications for large-scale systems
Related Videos
- Charting Architectural Innovation in the Chiplet Era with OCP's Cliff Grossner
- Standards for Chiplet Design with 3DIC Packaging (Part 1)
- Standards for Chiplet Design with 3DIC Packaging - Part 2
- Accelerating AI Innovation with Arm Total Design: A Case Study
Latest Videos
- Revolutionizing SoC Design: The Shift to Chiplet-Based Architectures
- Embedded World, Nuremberg: Arm’s Suraj Gajendra on AI, Chiplets, and the Future of Automotive Compute
- Keysight Expands Chiplet Interconnect Support with UCIe 2.0 & BoW
- Revolutionizing AI & Chiplets: Baya Systems CEO on $36M Series B, UALink, Future of Data Movement
- Machine Learning Applications in EDA for Chiplet Reliability