Breaking down 50 million pins: A smarter way to design 3D IC packages

How do you design and verify a package with tens of millions of pins without losing months to manual rework?

In this episode of the Siemens 3D IC Podcast, host John McMillan speaks with Per Viklund, Director of IC Packaging and RF Product Lines at Siemens EDA, about the growing challenge of managing chiplet and interposer complexity in advanced 3D IC designs.

Per explains how hierarchical device planning enables designers to work at the right level of abstraction, streamlining the creation, optimization, and verification of massive, high-pin-count packages.

The discussion covers why spreadsheet-based methods no longer cut it, the risks of unsynchronized workflows, and how early, multi-domain analysis can prevent costly late-stage redesigns.

The episode also introduces Siemens' Innovator 3D IC, a unified, AI-infused solution designed to support the entire packaging workflow, from early planning through final layout. It features built-in data management to eliminate version errors.