Speeding Up Die-To-Die Interconnectivity
Disaggregating SoCs, coupled with the need to process more data faster, is forcing engineering teams to rethink the electronic plumbing in a system. Wires don't shrink, and just cramming more wires or thicker wires into a package are not viable solutions. Kevin Donnelly, vice president of strategic marketing at Eliyan, talks with Semiconductor Engineering about how to speed up data movement between chiplets with bi-directional data movement, how to minimize signal integrity issues, and what other factors need to be considered.
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Videos
- Flexible eFPGA Based Demonstration Platform for Die-to-Die Interface Testing
- OCE Transaction and Link Layer Specification 1.2 Update
Latest Videos
- 2026 Predictions from Alpahwave Semi, now part of Qualcomm
- Arm Viewpoints: Chiplets explained – the technology and economics behind the next wave of silicon innovation
- The State of Multi-Die: Insights and Customer Requirements
- Coding approaches for increasing reliability and energy efficiency of 3D technologies
- AI-Driven Thermal Prediction for Enhanced Reliability in 3D HBM Chiplets