OCE Transaction and Link Layer Specification 1.2 Update
By Helia Naemi, Astera Labs and Brian Murray, Verisilicon
OCE Transaction and Link Layer Specification 1.2
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Videos
- Introducing the UCIe 2.0 Specification Supporting 3D Packaging and Manageability System Architecture
- The UCIe™ 1.1 Specification: Future Applications of Chiplets
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- Thermal Comparison between Monolithic and Chiplet ASIC Design
Latest Videos
- Advanced Packaging & Chiplet Design with Chipletz
- Integrated Photonics for the Next Generation of Glass Core Substrates
- Photonic Wire Bonding: Bridging the Gaps in Photonic Packaging
- Thermal Simulator for Advanced Packaging and Chiplet-Based Systems
- Cadence Chiplets Solutions: Helping you realize your chiplet ambitions