Monolithic 3D: Stacking Without Chiplets
By Dr. Ian Cutress, TechTechPotato
Chiplets aren't the only way forward in chip design. This deep dive explores an alternative that starts with layered logic — distributing circuits across tiers from the outset, not just stacking components after the fact. It begins in FPGAs at Georgia Tech, but the implications reach far beyond.
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Videos
- 3D Integration is Redefining the Semiconductor Landscape: MonolithIC 3D's Zvi Or-Bach
- AI-Driven Thermal Prediction for Enhanced Reliability in 3D HBM Chiplets
- How to accelerate innovation in IC technology with chiplets and 3D ICs
- The UCIe™ 1.1 Specification: Future Applications of Chiplets
Latest Videos
- Standardizing System-Level Interoperability for Multi-Vendor Chiplets
- Towards wafer-scale optical interconnect relying on Silicon Photonics and advanced 3D assembly
- Pre-Silicon Chiplet Verification for Datacenters
- Chiplets Modularity for AI and HPC
- Athos Silicon mSoC™ | A New Compute Architecture for Physical AI