I/O for Chiplets

One of the foremost questions in chiplet-based system design is interconnect: how to get signals between the chiplets. This question spans many layers of issues, from substrate choice to interface design to physical placement to test plans and control of unintended coupling between dies. But choices at these many layers interact. Integrating the tools for them is a work in progress, and design teams’ ability to deal gracefully with these challenges will determine the success or failure of the eventual vision: an open, off-the-shelf chiplet market.

These insights are courtesy of Toni Mastroianni, advanced packaging solutions director at Siemens EDA. The Ojo-Yoshida Report interviewed him for our Dig Deeper—Chiplets podcast series.