DAC 2025: Cadence and Its Ambition to Jumpstart the Chiplet Marketplace
At DAC 2025 in San Francisco, EE Times spoke to Michael Posner, senior product marketing group director for chiplet and IP solutions at Cadence Design Systems, to understand more about the company’s physical AI platform. The aim is to be able to mix and match heterogenous dies from different companies to enable the interoperability that would help jumpstart the chiplet marketplace.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- The Chiplet Market Today and Where It's Headed
- From OCP 2025: Arm’s Chiplet Push and the AI Ecosystem Play
- Splitting the Die A Modular Approach to Chiplet Design and Verification
- Exploring the Advancement of Chiplet Technology and the Ecosystem
Latest Videos
- Agile Silicon Will Open Chiplet Architectures Keep Pace with Fast-Evolving AI Dataflows
- One Abstraction, Many Transports: Push-Mode Communication from Chiplet to Rack
- Advancing Chiplet Flexibility Updates in 2.0 OCE Transaction and Link Layer Specification
- GTC '26 - Berlin | Long-running, multi-tool Fuse Agents for 3D IC workflows
- Securing the Open Chiplet Ecosystem Defining a Common Security Architecture for FCSA