D2D Chiplet Based SiP Testing Challenges and Solutions
By Mike Bartley, Alpinum and Boon Chong Intel
Chiplets are a new way to build System-in-Packages (SiPs) that can both improve yields and reduce costs. SiPs partition the system into discrete chiplets- assembles them within a package- and connect them using a standardized interface. This helps designers to meet performance- efficiency- power- size- cost- and quality (DPPM - Defective Parts Per Million) challenges in markets such as Automotive- 5/6G- VR- AI- and data centers. However- one bad die in a multi-die package can fail the whole SiP. The chiplet integration also requires testing and should enable a re-test of each chiplet in the SiP. This presentation focuses on achieving all this- starting with a problem statement to set the context.
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