Chiplet-Based Compressed LLC Cache & Memory Expansion

By Nilesh Shah, VP Business Development, Zeropoint Technologies

HBM memory chiplets, Non volatile memory chiplets, DDR memory over CXL and LLC cache chiplets help mitigate the infamous memory and SRAM scaling walls that limit compute performance in data centers and smart devices. However, chiplet based memory/ cache Total Cost of Ownership(TCO) currently limits deployment at hyperscale. A new hardware accelerated chiplet IP that compresses memory 2-4X in real time, at CACHE LINE granularities with sub 10ns latency can be integrated with SRAM LLC (Last Level Cache) chiplets, Nonvolatile memory chiplets and CXL connected memory chiplets, making the TCO more cost effective in terms of $$/GB without compromising performance. While this capability by itself is compelling, When coupled with a high speed coherent mesh network and protocol that can interconnect within an SoC, link independent processors into a chiplet and connect processor with main memory and I/O, tremendous return-on-investment and flexibility and efficiency in managing resources can be achieved. In this presentation, we detail out the Architectural building blocks that integrate with existing chiplet ecosystem components and have the potential to lower the memory and LLC cache chiplet adoption barrier for large memory applications in the Cloud, Hyperscale and Automotive segments. In our discussion, we pinpoint areas for collaborative innovation within the OCP ODSA Community to expedite software/hardware advancements for Chiplet based Memory Expansion. Furthermore, we delve into unresolved challenges in disaggregated coherent memory chiplet deployment and explore potential solutions.