Baya Systems AI-optimized chiplet interconnects at Embedded World 2025 WeaverPro, WeaveIP RISC-V HPC
At Embedded World 2025, Baya Systems showcased its approach to solving one of the biggest challenges in high-performance computing—efficient data movement. Nandan Nayampally, the company's Chief Commercial Officer, explained how Baya is addressing bottlenecks in intelligent compute acceleration by focusing on network infrastructure within chips. While traditional computing advancements have focused primarily on processing power, the real limitation today lies in how quickly data can move across different components. The company’s approach leverages chiplet-based architectures instead of monolithic system-on-chip (SoC) designs, creating modular, scalable systems that enhance data flow and computational efficiency.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- The Evolution of Chiplet Interconnects
- The Chiplet Problem No One Talks About
- Balaji Baktha, Paving the Road Ahead RISC V and Chiplet Technologies in Modern Automotive & More
- Bringing MOSA to C5ISR SOSA-aligned direct RF technology, RFS1140 Direct RF Chiplet
Latest Videos
- Advancing Chiplet Flexibility Updates in 2.0 OCE Transaction and Link Layer Specification
- GTC '26 - Berlin | Long-running, multi-tool Fuse Agents for 3D IC workflows
- Securing the Open Chiplet Ecosystem Defining a Common Security Architecture for FCSA
- Security of Multi chip ICs & Security Chiplets with Caliptra Building a Hardware Root of Trust
- System level standards for Multi vendor chiplet interoperability