Accelerating Chiplet Design with OCP Standards Compliant Chiplet Framework and Automation

Presenter: Michael Posner (Cadence Design Systems)

Heterogeneous, multi-die Systems-in-Package (SiPs) are increasingly common, bringing requirements for integration that go beyond traditional monolithic SoCs. This presentation offers a look at a framework aligned with OCP standards and an automation environment to accelerate the creation of interoperable chiplets. It demonstrates how using executable specifications and automated flows can shorten development cycles and reduce integration risks when working with chiplet-based systems.

The central framework extends the OCP Foundation Chiplet System Architecture, providing unified hardware and software management across chiplets, including boot, control, safety , security and debug. An automated workflow using YAML as its primary source, generates RTL code, IP-XACT, constraints, automated floorplans, documentation, C/C++ headers, and implementation and verification assets. Integrated generators assemble subsystems and configure IP modules.