Advancing Chiplet Flexibility Updates in 2.0 OCE Transaction and Link Layer Specification

Brian Murray, SoC Architect, VeriSilicon

This talk will cover an overview and new features of the 2.0 OCE Transaction and Link Layer Specification, which describes how SoC-native bus protocols can be transported over a chiplet D2D connection.  Updates include a universal PHY layer allowing designers to implement the same bus transport over UCIE, BoW, and the new BoW FLEXI physical layers.  This gives chiplet implementations much more flexibility in changing their D2D strategy without impacting the rest of the SoC design.   This also expands the options chip makers have in SoC disaggregation of subsystems into chiplets.

In addition, the talk will cover a variety of new 2.0 performance and efficiency features, changes to profiles, and tips for building new profiles for the standard.