Workflows for tackling heterogeneous integration of chiplets for 2.5D/3D semiconductor packaging

By John McMillan, Siemens

Keeping pace with Moore’s law continues to be a challenge and is driving the adoption of innovative packaging technologies that support continued system scaling. While doing so at costs less than comparable monolithic devices these packaging technologies disaggregate what would typically be a homogeneous or monolithic device like an ASIC or SoC into discrete unpackaged die known as chiplets. Today these devices are being designed and produced by a small number of advanced users. Broad industry proliferation will require the standardization of chiplet models along with the die-to-die connectivity IP – it will also necessitate workflows that support die package codesign.

What is a chiplet?

The chiplet is a die specifically designed and optimized for operation within a package in conjunction with other chiplets. This is also referred to as heterogeneous integration where multiple die or chiplets are integrated into a system in package (SiP).  These devices offer considerable benefits including performance, power, area, cost, and time to market.

Is heterogeneous packaging disruptive?

While heterogeneous integration offers many advantages it can also be disruptive to traditional design methods. Many Siemens customers are finding the need to evolve their methods and tools to fully leverage the benefits of heterogeneous integration.

Examples:

• Transition to system-based optimization from design-based optimization

• Expanding supply chain and tool ecosystems

• Balancing design resources across competing multi-domain requirements

What are the 3 enabling technologies for heterogeneous integration?

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