Why package lithography matters in heterogeneous chiplet integration
By Majeed Ahmad, EDN (December 13, 2023)
Digital lithography technology (DLT) is promising chipmakers to combine chips with submicron wiring on glass and other large substrates. And this maskless technology is at the center of a strategic partnership between Applied Materials and Ushio, aiming to accelerate the semiconductor industry’s transition to heterogeneous chiplet integration.
Applied Materials has been introducing materials, technologies, and systems that help chipmakers integrate chiplets into advanced 2.5D and 3D packages using hybrid bonding and through-silicon via (TSV) technologies. These initiatives complement heterogeneous integration (HI), which combines multiple chiplets in an advanced package with higher performance and bandwidth than a monolithic chip.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Technical Papers
- Five Workflows for Tackling Heterogeneous Integration of Chiplets for 2.5D/3D
- High-Efficient and Fast-Response Thermal Management by Heterogeneous Integration of Diamond on Interposer-Based 2.5D Chiplets
- Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration
- Complex Heterogeneous Integration Drives Innovation In Semiconductor Test
Latest Technical Papers
- Advances in waveguide to waveguide couplers for 3D integrated photonic packaging
- Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures
- DISTIL: A Distributed Spiking Neural Network Accelerator on 2.5D Chiplet Systems
- Multi-Partner Project: COIN-3D -- Collaborative Innovation in 3D VLSI Reliability
- EOTPR Fine Pitch Probing for Die-to-Die Interconnect Failure Analysis