Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links

By Stuart Daudlin ¹, Anthony Rizzo ^1,2,3, Sunwoo Lee ⁴,  Devesh Khilwani ⁴,  Christine Ou ⁴, Songli Wang ¹, Asher Novick ^{4, 1}, Vignesh Gopal ¹, Michael Cullen ¹, Robert Parsons ¹, Kaylx Jang ¹, Alyosha Molnar ⁴ & Keren Bergman ^1
1 Department of Electrical Engineering, Columbia University, New York, NY, USA.
² Air Force Research Laboratory Information Directorate, Rome, NY, USA. 
³ Thayer School of Engineering, Dartmouth College, Hanover, NH, USA. 4Department of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA.

Abstract

Artificial intelligence (AI) hardware is positioned to unlock revolutionary computational abilities by leveraging vast distributed networks of advanced semiconductor chips. However, a barrier for AI scaling is the disproportionately high energy and chip area required to transmit data between the chips. Here we present a solution to this long-standing overhead through dense three-dimensional (3D) integration of photonics and electronics. With 80 photonic transmitters and receivers occupying a combined chip footprint of only 0.3 mm², our platform achieves an order-of-magnitude-greater number of 3D-integrated channels than prior demonstrations. This enables both high-bandwidth (800 Gb s⁻¹) and highly efficient, dense (5.3 Tb s⁻¹ mm⁻²) 3D channels. The transceiver energy efficiency is showcased by a state-of-the-art 50 fJ and 70 fJ per communicated bit from the transmitter and receiver front ends, respectively, operating at 10 Gb s⁻¹per channel. Furthermore, the design is compatible with commercial complementary metal–oxide–semiconductor foundries fabrication on 300-mm-sized wafers, providing a route to mass production. Such ultra-energy-efficient, high-bandwidth data communication links promise to eliminate the bandwidth bottleneck between spatially distinct compute nodes and support the scaling of future AI computing hardware.

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