Temporary Direct Bonding by Low Temperature Deposited SiO2 for Chiplet Applications
By Koki Onishi (Yokohama National University), Hayato Kitagawa (Yokohama National University), Shunsuke Teranishi (Yokohama National University), Akira Uedono (Yokohama National University), and Fumihiro Inoue (Yokohama National University)
Die-to-wafer hybrid bonding is a crucial technology in advanced chiplet integration systems. Temporary die bonding on wafers and subsequent debonding are key aspects of this process. However, conventional polymer-based temporary bonding techniques involve several challenges such as issues related to the accurate placement of the die. Although direct bonding is a promising technology, such processes normally involve permanent bonds. The present study demonstrates an innovative temporary bonding method based on plasma-activated direct bonding and examines the associated bonding/debonding mechanisms. In this work, a dielectric bonding film was deposited at a relatively low temperature by chemical vapor deposition. This method offers several advantages, including high alignment accuracy, limited risk of die shift, and cost reduction based on removal of the carrier wafer grinding process. Wafer bonding was performed with SiO2 films deposited at low temperatures, and voids were formed at the bonding interfaces during postbond annealing. The bonding energy was sufficiently low even after annealing to allow wafer pairs to be released as a consequence of voids serving as initiation points for debonding. Desorption gas analysis established that the SiO2 films absorbed significant moisture from ambient air, which was the root cause of void formation. Die-to-wafer bonding tests confirmed the formation of voids at the bonding interfaces. This dielectric is likely to have applications as a temporary bonding material in chiplet integration systems.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Technical Papers
- Thermal stability enhancement of low temperature Cu-Cu bonding using metal passivation technology for advanced electronic packaging
- Hybrid surface pre-treatments for enhancing copper-to-copper direct bonding
- High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions
- Optimized Low Parasitic Capacitance ESD Clamps for High-Bandwidth 2.5D/3D Chiplet Interfaces in Advanced FinFET Technology
Latest Technical Papers
- Link Quality Aware Pathfinding for Chiplet Interconnects
- Effects of Poor Workload Partitioning on System Performance for Chiplet-Based Systems
- Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures
- Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding
- CarbonPATH: Carbon-aware pathfinding and architecture optimization for chiplet-based AI systems