Self-Attention to Operator Learning-based 3D-IC Thermal Simulation
By Zhen Huang 1,2, Hong Wang 1, Wenkai Yang 3,5, Muxi Tang 4, Depeng Xie 5, Ting-Jung Lin 2, Yu Zhang 1, Wei W. Xing 6, Lei He 2,7
1 School of Computer Science and Technology, University of Science and Technology of China, Hefei, China
2 Ningbo Institute of Digital Twin, Eastern Institute of Technology, Ningbo, China
3 ShanghaiTech University, Shanghai, China 4 Tsinghua University, Beijing, China
5 BTDTechnology, Ningbo, China 6 University of Sheffield, Sheffield, UK
7 University of California, Los Angeles, USA

Abstract
Thermal management in 3D ICs is increasingly challenging due to higher power densities. Traditional PDE-solving-based methods, while accurate, are too slow for iterative design. Machine learning approaches like FNO provide faster alternatives but suffer from high-frequency information loss and high-fidelity data dependency. We introduce Self-Attention U-Net Fourier Neural Operator (SAU-FNO), a novel framework combining self-attention and U-Net with FNO to capture long-range dependencies and model local high-frequency features effectively. Transfer learning is employed to fine-tune low-fidelity data, minimizing the need for extensive high-fidelity datasets and speeding up training. Experiments demonstrate that SAU-FNO achieves state-of-the-art thermal prediction accuracy and provides an 842x speedup over traditional FEM methods, making it an efficient tool for advanced 3D IC thermal simulations.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Technical Papers
- DeepOHeat-v1: Efficient Operator Learning for Fast and Trustworthy Thermal Simulation and Optimization in 3D-IC Design
- Thermal Issues Related to Hybrid Bonding of 3D-Stacked High Bandwidth Memory: A Comprehensive Review
- ATSim: A Fast and Accurate Simulation Framework for 2.5D/3D Chiplet Thermal Design Optimization
- Spatiotemporal thermal characterization for 3D stacked chiplet systems based on transient thermal simulation
Latest Technical Papers
- Mapping Space Exploration for Multi-Chiplet Accelerators Targeting LLM Inference Serving Workloads
- Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
- 3D optoelectronics and co-packaged optics: when solving the wrong problems stalls deployment
- Expert Streaming: Accelerating Low-Batch MoE Inference via Multi-chiplet Architecture and Dynamic Expert Trajectory Scheduling
- WarPGNN: A Parametric Thermal Warpage Analysis Framework with Physics-aware Graph Neural Network