Toward Multi-kW Power Delivery Methodologies for Advanced 3D Heterogeneous Integration
By Peiyi Yue, Hangyu Zhang, Ratul Das, Ramesh Harjani, Sachin S. Sapatnekar
University of Minnesota, Minneapolis, USA

Abstract
The demands of modern applications require the construction of ever more complex integrated systems, with AI applications in particular serving as a significant driver for increased system size, potentially going beyond the trilliontransistor mark. The path to building these systems requires the use of advanced packaging, with heterogeneous integrated 2D and 3D chiplets placed atop a substrate. Such computationally powerful systems require significant power for computation: reliable and robust power delivery is a major challenge in light of high power densities and pin count bottlenecks. This paper overviews approaches to building design methodologies that overcome this problem, through the design of multistage distributed power delivery systems, optimized for performance and reliability, and built to coexist within stringent performance, thermal, and reliability constraints.
Keywords: Power delivery, 3D integrated circuits, 2.5D, advanced packaging, heterogeneous integration, voltage regulators.
To read the full article, click here
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related Technical Papers
- Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators
- 3D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency
- GPU-Accelerated Effective Resistance Analysis for 3D IC Power Delivery Network
- 3D Integration, Advanced Metrology Shape the Semiconductor Landscape
Latest Technical Papers
- Toward Multi-kW Power Delivery Methodologies for Advanced 3D Heterogeneous Integration
- Cu-Cu Hybrid Bonding for Chiplets Heterogeneous Integration
- Location-Aware Caching Mechanism for minimizing performance degradation induced by inefficient inter-chiplet data path
- Predicting Cure Evolution and Thermal Endurance of a Highly Filled Epoxy Underfill for Advanced Packaging
- A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System