Optimizing Wafer Edge Processes For Chip Stacking

By Laura Peters, SemiEngineering (September 23rd, 2024)

Several critical processes address wafer flatness, wafer edge defects and flatness to enable bonded wafer stacks.

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligable levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption.

The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stacks in HBMs. Vertical stacking allows chipmakers to leapfrog the interconnection pitch from 35µm in copper micro-bumps to 10µm and below.

But going vertical comes at a cost, which has left chipmakers scrambling to find ways to reduce wafer-edge defects. Those defects significantly impede the ability to yield all die on the wafer, and the need to bond wafers together calls for incredibly flat, defect-free 300mm wafers. To better control wafer-edge defects throughout fab processing, and for fusion and hybrid bonding, engineers are fine tuning new and existing processes. These include a symphony of techniques involving both wet and dry etching at the wafer edge, chemical mechanical polishing (CMP), edge deposition, and edge trimming steps.

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