As Chips Go Vertical, Metrology Struggles to Keep Up

Advanced-node manufacturing is pushing semiconductor inspection beyond traditional top-down measurement and toward reconstructing buried 3D structures that conventional tools can no longer easily see.

By Pat Brans, EE Times | June 9, 2026

Semiconductor inspection has traditionally meant looking down. Optical metrology and critical dimension scanning electron microscopy (CD-SEM) systems were optimized for lateral scaling, where the central challenge was shrinking dimensions across the surface of silicon. That approach worked when transistor architectures remained relatively planar and accessible.

Today, however, advanced-node manufacturing is moving increasingly into the Z-axis. Gate-all-around transistors, recessed nanosheets, HBM memory, vertically stacked NAND, hybrid bonding, and future CFET architectures are creating structures that are narrower, deeper, and more difficult to inspect. Critical variability increasingly exists along buried sidewalls and recessed regions rather than only on the top surface of the device.

“Scaling is no longer happening only in the X-Y plane, but increasingly in the Z direction,” Philippe Leray, VP of advanced patterning at imec, told EE Times. “More and more, we need to look deep inside these structures to characterize defects, composition, roughness, and dimensional variation.”

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