Zero ASIC releases PackageCompiler, the world’s first fully autonomous chip package compiler.

Cambridge, MA – June 9, 2026 – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced the release of PackageCompiler™, the world’s first fully autonomous chip package compiler.

Background

Moore’s Law has enabled decades of relentless progress through transistor scaling and monolithic integration. However, with per-transistor cost reductions stalling and design complexity exploding, leading semiconductor companies are increasingly adopting disaggregated architectures (aka. chiplets).

When we founded Zero ASIC with the mission of creating an open, composable chiplet ecosystem, we quickly discovered that existing package design tools were woefully inadequate. While digital IC design has benefited from decades of investment in automated place-and-route technology, package and substrate design remains largely manual, error-prone, and time-consuming. Engineers still spend countless hours pushing polygons by hand in tools that were never designed for the bump counts, layer stacks, and complex 3D topologies of modern chiplet-based systems.

On reflection we realized that the industry was not going to build the class of automation required to realize our vision of democratized silicon. Rather than wait for the ecosystem to catch up, we decided to build the tools ourselves…

Architecture

PackageCompiler was built around a simple belief: package design should be treated as a software compilation problem, not a manual drafting exercise. By combining a unified 3D data model, automated implementation, and massively parallel optimization, PackageCompiler enables engineers to design complex chiplet systems with a level of productivity and scalability that traditional package design tools were never built to achieve.

PackageCompiler Principles:

• Automation first: PackageCompiler is a compiler, not a GUI.
• Open by default: all interfaces, standards, and data formats should be open.
• Parallel everywhere: leverage GPUs, many-core CPUs, and cloud-scale compute.
• Database unification: a unified design and layout database built for 3D.
• Zero installation: accessible from any modern web browser.

At the heart of PackageCompiler is a unified data model that captures both the logical and physical views of a design. The logical hierarchy describes modules, instances, and nets in a Verilog-like structure, while the physical hierarchy describes layers, components, pad stacks, pins, and routing. This separation allows PackageCompiler to reason about connectivity and geometry together, the foundation required for true layout-versus-schematic correctness across an entire system.

The compiler takes a system from specification to manufacturing-ready outputs with minimal human intervention. The designer describes a package in a concise YAML/JSON design specification, and PackageCompiler handles substrate layout generation, routing, design-rule validation, and export to industry-standard formats such as KiCad and Gerber.

Correct-by-construction is reinforced by an integrated validation module that performs traditional DRC and LVS style checks, catching opens and shorts before a design is ever sent out for fabrication. Combined with a browser-based design viewer built on modern web standards and 3D visualization, PackageCompiler gives engineers a complete, autonomous flow from specification to silicon-ready package.

PackageCompiler was architected from day one to natively support 3D silicon topologies. Using the open 3Dblox standard alongside industry formats such as LEF/DEF and structural Verilog, designers can describe multi-die assemblies that stack chiplets on interposers and substrates, with shared power and ground networks and per-die signal connectivity. This 3D-native approach has been battle tested on in-house chiplet designs containing more than 50,000 bumps.

Layout automation is handled via an autonomous layout engine, deep_route, that acts as a lightning fast general purpose incterconnect router. Traditional package routers search for a route. Deep Route searches for routing strategies. Strategies scale, and by leveraging massively parallel search across many cores, deep_route is able to tackle the congestion and crossing problems that make package routing so difficult. The engine incorporates a number of novel techniques, including signed distance field based routing, force-field trace smoothing, and parameter optimization, to produce high quality, manufacturable interconnect.

Attribute	Traditional Package EDA	PackageCompiler
Autonomous Routing	No	Yes
3D / Stacked Silicon	Limited	Yes
Spec-Driven Design	No	Yes
Browser-Based Viewer	No	Yes
Open Standards	Partial	Yes

Supported Formats

PackageCompiler interoperates with a broad set of open standardized design and layout formats.

Format	Direction	Description
YAML/JSON	Input	Design specification driving the compiler
3Dblox	Input	3D system-in-package and multi-die assemblies
LEF/DEF	Input	Industry-standard IC physical design exchange
Verilog	Input	Structural netlists for logical connectivity
BMap	Input	Columnar bump and ball map assignments
ZPDK	Input	Native PDK format for layer stacks and design rules
KiCad	Output	Open source PCB/package design exchange
Gerber	Output	Manufacturing-ready fabrication data

Availability

PackageCompiler is currently available to Zero ASIC chiplet customers and partners. In line with our mission to democratize silicon, we also are launching a public beta for the broader engineering community. To get beta access, visit https://zeroasic.com/packagecompiler.

About Zero ASIC

Zero ASIC is a semiconductor startup based in Cambridge, Massachusetts. The company mission is to democratize access to silicon through chiplets and design automation. Zero ASIC is building the world’s first composable chiplet platform, enabling billions of unique silicon systems to be assembled in hours from a catalog of off-the-shelf chiplets.