D2D Chiplet Based SiP Testing Challenges and Solutions

By Rajesh Pendurkar, Capgemini Engineering and Aparna Tard,  Synopsys

In multi-die packages- one bad die can result in the failure of the whole package. Heterogenous integration complexities drive the need for effective inspection for high yields and long-term reliability. Product defects needs to be caught early in the production phase. The high-performance computing system-on-chip (SoC) in the hyperscale data center- networking- and AI applications cannot tolerate product defects. Test methodologies are needed to standardize and improve production test speed & coverage.\nThis paper outlines chiplet testing challenges and offers solutions based on DFT standards compliance- robust test architectures- advanced functional testing methodologies- and collaboration among chiplet vendors- designers- and test engineers. The paper highlights chiplet testing challenges and solutions to enable efficient production test of system-in-packages (SiPs) using die-to-die interfaces and ensuring high production yield.