Chiplets for Neuromorphic Computing
By Johannes Schemmel, Heidelberg University
Event-based neuromorphic computing is a promising technology for energy-efficient bio-inspired AI. It also enables continuous learning based on local learning algorithms. For maximum energy efficiency, a brain-like in-memory realization is desirable. The Heidelberg BrainScaleS platform is an example of a Neuromorphic architecture that combines true in-memory computing with hardware support for continuous local learning. For real-world applications as well as neuroscience, some minimum network sizes are required. To realize the necessary upscaling, BrainScaleS has invented Wafer Scale integration. For the future generations of BrainScaleS, this will not be feasible due to high mask-costs of modern semiconductor processes. This talk presents an alternate solution based on Chiplet technology. It introduces concepts that not only allow to scale BrainScaleS-based networks but will also provide a general platform for upscaling all kinds of neuromorphic technologies.
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Videos
- Chiplets: The Future for Computing
- What's Next for Chiplets
- I/O for Chiplets
- Chiplets for generative AI
Latest Videos
- Accelerate 3D IC designs with Innovator3D IC
- On Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low-Power, High-Bandwith, Low-Latency and Low-Cost Approach
- Breaking down 50 million pins: A smarter way to design 3D IC packages
- Optimizing Data Movement in SoCs and Advanced Packages
- Cache Coherency in Heterogeneous Systems