Workload-Specific Hardware Accelerators
Workload-specific hardware accelerators are becoming essential in large data centers for two reasons. One is that general-purpose processing elements cannot keep up with the workload demands or latency requirements. The second is that they need to be extremely efficient due to limited electricity from the grid and the high cost of cooling these devices. Sharad Chole, chief scientist and co-founder of Expedera, talks with Semiconductor Engineering about the role of neural processing units inside AI data centers, tradeoffs between performance and accuracy, and new challenges with chiplet-based multi-die assemblies.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- Compression Enabled MRAM Memory Chiplet Subsystems for LLM Inference Accelerators
- Blueprint for AI Hardware But with Instructions: Pre-Validated Chiplet Building Blocks
- Security of Multi chip ICs & Security Chiplets with Caliptra Building a Hardware Root of Trust
- Custom HBM as a System: Co-designing the Base Die, Die to Die Power, and Package Thermals for AI Accelerators
Latest Videos
- The European Chip Ecosystem
- Scaling up AI Compute, Memory and Connectivity
- CURIE: A Cycle-Accurate and Synthesizable UCIe Interface for the Agile Design and Co-Simulation of Chiplets
- Federated Chiplet Design and Simulation
- Custom HBM as a System: Co-designing the Base Die, Die to Die Power, and Package Thermals for AI Accelerators