Die to Die Solutions for Optical Chiplets
Kevin Donnelly, VP, Eliyan
During the last two decades, increases in compute performance in FLOPs has far outpaced the increases in interconnect bandwidth, leading to limitations in system performance often described as the I-O Wall. System designers are evaluating a wide range of optical technologies to enable optical scale-up and scale-out solutions for datacenters. Optical solutions connect to XPUs via electrical interfaces, and as optics move ever closer to the XPU with co-packaged optics (CPO), designers are evaluating different die-to-die (D2D) interfaces for these ASIC-to-optical connections. This talk will describe several electrical-to-optical connection examples with D2D solutions including UCIe, BoW, and 3D PHY interfaces, and show how these D2D interfaces can enable different system-level solutions. D2D interfaces can efficiently connect ASICs to optical devices, providing improved performance at lower power than traditional off-package SerDes interfaces to optical modules.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- Breaking Down Die Size Barriers with Chiplets
- Splitting the Die A Modular Approach to Chiplet Design and Verification
- Photonic Fabric Interface Chiplets for AI XPU Optical Connectivity
- Mark Wade of Ayar Labs: We Solve AI data Movement Challenges with Optical Chiplets
Latest Videos
- Die to Die Solutions for Optical Chiplets
- Building Interoperable AI Systems with Chiplets Arm Neoverse and Cadence in an Open Ecosystem
- Market Forecast for CPO and NPO
- Mark Papermaster at World Summit AI 2026 Talks Holistic Computing, Chiplets and AI Sovereignty
- Accelerating Chiplet SoC Development with Standards-Based Frameworks and Automated Design Flows