Advanced Packaging: Enabling AI at Scale
Presenter: CP Hung, Vice President of Corporate R&D, ASE
The future of AI infrastructure will not be defined by silicon alone. As AI workloads drive unprecedented demand in hyperscale data centers and high-performance computing (HPC), advanced packaging has become a critical enabler of system performance, energy efficiency, and scalability. Heterogeneous integration, chiplets, and advanced packaging technologies are bringing together compute, memory, and high-speed interconnects to overcome bandwidth, power, and thermal challenges that increasingly define next-generation AI platforms.During his keynote, CP Hung will explore how breakthroughs in heterogeneous integration, chiplets, and advanced manufacturing are transforming bold AI ambitions into deployable systems. He will discuss how advanced packaging is enabling the AI infrastructure behind hyperscale data centers and HPC, and why future AI leadership will depend not only on compute performance, but on the ability to integrate and manufacture complex systems at scale.
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related Videos
- Podcast - A Modular Future: Chiplets, AI, and Advanced Packaging
- Propelling AI forward through Advanced Packaging Creativity
- Moving Data at the Speed of AI
- Live with Cadence talking AI, Chiplets, Virtual Prototyping and more at Embedded World 2024
Latest Videos
- Accelerating Chiplet Design with OCP Standards Compliant Chiplet Framework and Automation
- Chiplet Identity and Roots of Trust in FCSA Systems: An Architecture-Agnostic Security View
- From Transistors to AI: The Chiplet Revolution with Ramune Nagisetty
- Scaling AI with Chiplets & CPO
- Open Interconnect Innovations: A Deep Dive into the UALink Chiplet Specification Tutorial