Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures

By Zizhen Liu ¹, Fangzhiyi Wang ^1,2, Mengdi Wang ¹, Jing Ye ^1,2,3, Hayden Kwok-Hay So ⁴, Cheng Liu ^1,2, Huawei Li ^1,2,3
1 State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences
² University of Chinese Academy of Sciences
³ CASTEST Co., Ltd.
⁴ School of Innovation, The University of Hong Kong

Abstract

The growing demand for compute-intensive applications has made multi-chiplet architectures a promising alternative to monolithic designs, offering improved scalability and manufacturing flexibility. However, effectively managing the economic effectiveness remains challenging. Existing cost models either overlook the amortization of compute value over a chip's operational lifetime or fail to evaluate how redundancy strategies, which are widely adopted to enhance yield and fault tolerance, impact long-term cost efficiency. This paper presents a comprehensive cost-effectiveness framework for multi-chiplet architectures, introducing a novel Lifecycle Cost Effectiveness (LCE) metric that evaluates amortized compute costs by jointly optimizing manufacturing expenses and operational lifetime. Our approach uniquely integrates: (1) redundancy-aware cost modeling spanning both intra- and inter-chiplet levels, (2) reliability-driven lifetime estimation, and (3) quantitative analysis of how redundancy configurations on overall economic effectiveness. Extensive trade-off and multi-objective optimization studies demonstrate the effectiveness of the model and reveal essential co-optimization strategies between module and chiplet-level redundancy to achieve cost-efficient multi-chiplet architecture designs.

Index Terms — chiplets, cost-effectiveness, redundancy

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