Die-Level Transformation of 2D Shuttle Chips into 3D-IC for Advanced Rapid Prototyping using Meta Bonding

Three-dimensional integrated circuit (3D-IC) technology, often referred to as through-silicon via (TSV) formation technology, has been steadily maturing and is increasingly used in advanced semiconductor devices such as 3D complementary metal-oxide-semiconductor image sensors, high-bandwidth memory, and static random-access memory on central processing units (commonly known as 3D V-Cache). However, the initial development costs remain prohibitively high, primarily due to the substantial investment required for TSV formation at the wafer level. Meanwhile, conventional system-on-chip designs are transitioning from fin field-effect transistor to gate-all-around architectures using the latest sub-3 nm technology nodes and incorporating extreme ultraviolet lithography along with other cutting-edge techniques. Simultaneously, the academic community is fostering an environment that supports technology node utilization from legacy 180 to 7 nm, enabling designers to develop two-dimensional IC (2D-IC) chips with novel architectures at reduced costs. Despite these advancements, foundry shuttle services utilizing TSVs remain largely inaccessible, making proof-of-principle demonstrations and functional verification using 3D-ICs extremely challenging. This study introduces recent technological advancements that enable the transformation of 2D-ICs into 3D-ICs using shuttle chips from multi-project wafers, ranging from small to large-scale implementations. The discussion primarily focuses on die-level, short-turnaround-time 3D-IC fabrication, emphasizing key enabling technologies such as multichip thinning and TSV/microbump formation. In addition, the study explores the effectiveness of Meta Bonding techniques, including fine-pitch microbump, direct bonding, and hybrid bonding, for future high-performance 3D-IC prototyping.