Chiplet-NAS: Chiplet-aware Neural Architecture Search for Efficient AI Inference on 2.5D Integration
By Cheng Guo 1, Pragnya Sudershan Nalla 2, Nikhil Kumar Cherukuri 2, Rui Xue 3, Sachin S. Sapatnekar 2, Chaitali Chakrabarti 1, Yu Cao 2, Jeff Zhang 1
1 Arizona State University
2 University of Minnesota
3 Independent Researcher
Abstract
The co-design of neural network architectures and their target chiplet-based hardware systems presents a significant challenge due to the vast and combinatorial design space. Identifying solutions that are Pareto-optimal across competing objectives of task accuracy, system latency, and power consumption requires solutions beyond manual design and brute-force methods. This paper proposes a closed-loop chiplet-aware neural architecture search (Chiplet-NAS) framework to automate the exploration and discover hardware-optimized models for efficient AI inference on 2.5D chiplet-based systems. The framework integrates a Tree-structured Parzen Estimator (TPE) for sample-efficient search with CLAIRE, a chiplet-based library and fast performance benchmarking tool, to provide direct hardware feedback on latency and energy consumption, along with accu racy optimization. The framework is evaluated by co-designing ResNet-based model architectures with chiplet based hardware systems. Compared to a baseline NAS that optimizes only on the task accuracy, our Chiplet-NAS achieves significant power and performance benefits at the iso-accuracy.
Index Terms — Chiplets, Neural Architecture Search, 2.5D Integration, Heterogeneous Integration
To read the full article, click here
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Technical Papers
- DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications
- A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models
- Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
- Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM
Latest Technical Papers
- Beyond Host-Side Control: HBM Controller Partitioning Across Host and HBM Base Dies
- Chiplet-NAS: Chiplet-aware Neural Architecture Search for Efficient AI Inference on 2.5D Integration
- Scaling Up Analog CIM: A Simulation Framework for Topology-Aware Mapping
- AI-Based Image Enhancement Improves Detection of Interconnect Defects in Microelectronic Packaging
- Embodied Emissions of 2.5D and 3D Scaling in Chipletized GPUs for Low-Carbon AI