Adaptive 3D Chiplet Architecture with Hybrid Wired–Wireless Interconnect for Energy-Efficient Heterogeneous Computing
By Ch. Sreedhar 1, Dr. Ch. Raja 2, Dr. Amit Jain 3
1 Shri Venkateshwara University
2 Mahatma Gandhi Institute of Technology
3 Inderprastha Engineering College
Abstract
Chiplet integration provides a scalable alternative to monolithic system-on-chip design, but the decomposition of a large die introduces a communication penalty arising from die-to-die interfaces, inter-chiplet distance, routing hops, and packaging overhead. This paper develops an adaptive three-dimensional (3D) chiplet architecture that combines decomposition-aware chiplet selection, vertically stacked compute–memory organization, and a hybrid wired–wireless interconnection fabric. The proposed architecture retains conventional wired Network-on-Chip (NoC) links for localized deterministic traffic while providing wireless express links for long-distance, multicast, and broadcast communication. A latency-aware routing mechanism estimates wired and hybrid path costs and selects the lower-cost route subject to traffic and congestion conditions. The evaluation is deliberately literature-grounded: the uploaded baseline study reports 8–46% average end-to-end latency reduction, 0.93–2.7× energy savings, 13.9% hybrid-router area overhead, and a 43% energy-efficiency advantage for larger chiplets in a decomposition study. These values are treated as reported evidence rather than new silicon measurements. The proposed integration is therefore positioned as a reproducible architectural framework whose next validation step is cycle-accurate full-system simulation and thermal-aware 3D analysis. The resulting design targets AI, high-performance computing, and heterogeneous edge workloads where communication intensity and synchronization dominate system-level efficiency.
Keywords: Chiplets; 3D integration; heterogeneous computing; hybrid NoC; wireless NoC; adaptive routing; TSV; energy efficiency; die-to-die communication.
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