Signal Integrity Designs at Organic Interposer CoWoS-R for HBM3-9.2Gbps High Speed Interconnection of 2.5D-IC Chiplets Integration
May. 30, 2024 -- Congratulations on the GUC's paper acceptance by IEEE and our member's invitation to present at the 74th ECTC on May 31st, 2024.
We (GUC) will present our high speed integrated design (signal integrity) solution for HBM3E-9.2Gbps on organic interposer technology. The paper will also be filled at IEEE Xplorer Digital Library (https://ieeexplore.ieee.org/Xplore/home.jsp). (The link will be updated after the 74th ECTC)
Paper Title: Signal Integrity Designs at Organic Interposer CoWoS-R for HBM3-9.2Gbps High Speed Interconnection of 2.5D-IC Chiplets Integration
Content
- Introduction
- HBM3 SI Design Flow and Optimization
- The proposed GSG-interleaved T-lines at CoWoS-R
- HBM3 High Speed Interconnection Design
- Design-of-Experiments at Interconnect Routing Rules
- Interconnect Post-Layout Simulation
- Insertion loss / Crosstalk Characterization
- FoMsof High Speed Interconnect Design
- Eye-diagram Co-Simulation
- Measurement and Correlation
- Conclusion
Remark
IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
Remark
The Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the IEEE Electronics Packaging Society.
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- Alphawave Semi Highlights Why the Next Generation of AI Advances Demand Chiplet Architectures at EE Times: The Future of Chiplets
- The Future of Chip Integration: Fraunhofer IPMS Develops High-Density Chiplet Systems at the Wafer Level
- EV Group Highlights Hybrid Bonding, Layer Transfer and Maskless Lithography Technologies for Heterogeneous Integration and Advanced Packaging at ECTC 2026
- Understanding 3DIC, Heterogeneous Integration, SiP, and Chiplets at Once
Latest News
- Imec unlocks system-level III-V chiplet integration on Si-CMOS by advancing its 300mm RF silicon interposer platform with high-density MIMCAPs, passive modeling, and laser-assisted bonding
- CoAsia SEMI Unveils Advanced Strategy for Next-Generation Chiplet Platform 'CoCs™' at Samsung SAFE Forum
- JCET Launches Next-Generation Power Module Packaging and Test Solutions for AI Data Centers
- As Chips Go Vertical, Metrology Struggles to Keep Up
- Silicon Box Secures SGD 100M Financing to Accelerate Growth in Advanced Packaging