Bring Your Own RTL to Zero ASIC's Chiplet Ecosystem

By Zero ASIC

March 19, 2024

Today, Zero ASIC is releasing a demo that shows how to create a custom EBRICK, a chiplet that can plug into our SiP design ecosystem. The demo can be found on GitHub at https://github.com/zeroasiccorp/ebrick-demo.

EBRICKs are chiplets with a standard interface and standard sizes, making it possible to mix and match them on a general-purpose silicon interposer. Zero ASIC is currently developing a catalog of standard EBRICKs, including a RISC-V CPU, a machine learning accelerator, and an FPGA. By combining these standard chiplets with a custom EBRICK containing the "secret sauce" for an application, high-performance hardware products can be developed in a cost- and time-efficient manner.

In the demo, we show how our tools switchboard and SiliconCompiler make it easy to verify a custom EBRICK design and generate a physical implementation. The intent is that the demo repository may be used as a template for building custom EBRICKs, where the demo logic is replaced with a user's custom logic.

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