When the Package Becomes an Electrical Design Variable
The most critical electrical path in an AI server may also be the shortest. In advanced AI systems, voltage stability is no longer determined solely by the board-level power delivery network (PDN). As more functionality moves into advanced packages, the package itself has become an integral part of the PDN.
The board still distributes power across the system, but voltage stability at the processor increasingly depends on what happens inside the package. Parasitic inductance, integration density, and the distance between decoupling capacitance and the point of load all influence how effectively the PDN can suppress transient voltage droop.
To read the full article, click here
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related Blogs
- The Next-Generation UCIe IP Subsystem for Advanced Package Designs
- When EMC Shielding Must Bend With the Package
- 3D IC design for the AI era: an EDA perspective
- The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation
Latest Blogs
- Chiplet Modularity Is Becoming Part of the AI Architecture
- Hierarchies Of Interconnects Are As Important As Compute And Memory
- UALink over UCIe 3.0: Maximizing Performance for Chiplet-based Designs
- Physical AI Doesn't Just Scale Up. It Scales Out.
- Ayar Labs and GUC Complete Successful Thermal Co-Simulation Testing of Co-Packaged Optics