Arm Ecosystem Collaborates on Standards to Enable a Thriving Chiplet Market
By Richard Grisenthwaite, EVP, Chief Architect & Fellow, Arm
Arm and ecosystem partners are looking to accelerate the next evolution of silicon.
A key challenge our partners are consistently looking to solve is: How can we continue to push performance boundaries, with maximum efficiency, while managing costs associated with manufacturing and yield? Today, as the ever more complex AI-accelerated computing landscape evolves, a key solution emerging is chiplets.
Chiplets are designed to be combined to create larger and more complex systems that can be packaged and sold as a single solution, made of a number of smaller dies instead of one single larger monolithic die. This creates interesting new design possibilities, with one of the most exciting being a potential route to custom silicon for manufacturers who historically chose off-the-shelf solutions. The excitement is focused on the concept of composability – putting together a bespoke complete solution by reusing a set of existing or standardized chiplets, each optimized for cost-performance. This reusability and standardization can lead to a multi-vendor chiplet supply chain that could enable both new and existing players to access performance and differentiation opportunities.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Blogs
- Arm Ecosystem Collaborates on Standards to Enable a Thriving Chiplet Market
- Accelerating an Open Chiplet Ecosystem for Automotive with Foundation Chiplet System Architecture
- UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
- Podcast: How Achronix is Enabling Multi-Die Design and a Chiplet Ecosystem with Nick Ilyadis
Latest Blogs
- Building out the Photonic Stack
- 2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics
- Accelerating Chiplet Integration in Heterogeneous IC Package Designs
- Visualizing Cross-Die Paths in Multi-Die Designs
- 5 Chiplets Design Challenges Hampering Wider Take-off